• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:

    公开号:BE1019752A3
    申请号:E201000469
    申请日:2010-07-29
    公开日:2012-12-04
    发明作者:Pierre Fereyre；Vincent Hibon；Yann Henrion；Patrick Lariviere
    申请人:E2V Semiconductors；
    IPC主号:
    专利说明:

    CONNECTION PLATE STRUCTURE FOR ELECTRONIC COMPONENT
    The invention relates to the manufacture of electronic components on thinned semiconductor substrate. It will be described mainly about an image sensor on thinned silicon substrate, illuminated by the rear face.
    Image thinned image sensors have been designed in particular to improve colorimetric performance by allowing the illumination of the sensor by the rear face of a very thin silicon layer.
    The manufacture of an image sensor on a thinned substrate generally comprises the following steps: starting from a normal silicon substrate, with a thickness of a few hundred micrometers, allowing industrial handling of collective slices of about ten to twenty centimeters in diameter, this substrate being coated, on a front face, with an epitaxial layer of monocrystalline silicon, optionally isolated from the rest of the substrate by an oxide layer in the case of so-called SOI substrates ("Silicon on insulator" in English). On the front face of this monocrystalline layer, the electronic circuitry necessary for the various functions of the sensor (essentially image capture) is produced. Then the substrate is bonded, by its front face which carries this circuitry, on a transfer substrate of a sufficient thickness for industrial handling, and the starting silicon substrate is thinned to a thickness of a few micrometers. The very thin thickness of silicon that results would not allow the industrial handling of the wafer, and this is the reason for the presence of the bonded or welded transfer substrate.
    One of the problems that arise for these components is the formation of connection pads, for the connection of the component with the outside. The assembly of the component in a housing generally requires solder wires connecting a metal connection pad provided on the component and metal pads provided in the housing.
    Since the substrate in which the electronic circuits have been formed has been bonded by its front face to a transfer substrate, the front face is no longer accessible. It is therefore sought to establish a connection by the rear face by digging the thinned substrate, until finding a conductive pad which has been formed beforehand during the ^ manufacturing steps by the front face.
    In particular, it is possible to dig the silicon and the insulating layers that have been formed on the front face until reaching the first level of aluminum. A gold connection wire is then soldered by the conventional "wire-bonding" technique on the exposed aluminum strip. But this beach is located in a bowl since it was necessary to dig the silicon and insulating layers that covered it. This precludes the use of "wedge bonding" as opposed to "bail bonding" wire welding methods in which the wire (usually aluminum) to be welded is too obliquely to be welded inside a wire. bowl. That is why we are forced to continue to use a gold wire weld, even in cases where we prefer a wire of aluminum. In addition, the bowl is formed in a semiconductor material and non-insulating, and there is therefore a risk of short circuit between the wire and the edges of the bowl, except to isolate the flanks, which complicates the implementation.
    Furthermore, it should also be noted that the aluminum strips used for soldering wires must in principle be thicker than the aluminum layers that are used for ordinary interconnection functions in the integrated circuit. However, the technique explained above allows in practice to access only the first level of aluminum (except to want to dig even deeper), and this level has no reason to be thick enough to allow a weld. To adapt this solution to an industrialization, it would therefore be necessary to provide a first level of aluminum that is thicker than what is generally necessary; this requires changing the standard manufacturing process, which is not desirable.
    On the other hand, the manufacture of integrated circuits requires electrical tests by spike test machines. The test tips are applied to access pads of the integrated circuit. These studs can be specifically provided for the test, but in practice it will also be used later to solder connection son. It is desirable to be able to test the integrated circuit after the manufacturing steps made on the front face, and to be able to test it again by the rear face after gluing and thinning. And, if it is possible, it would be advantageous to be able to test the rear face with the same configuration of test tips that was used at the end of the manufacturing steps performed on the front panel.
    This means that it is necessary to manufacture on the front face test pads which have the same geometrical configuration or at least the same geographical position as the outer connection pads of the rear face. As a result, at the point of the connection pads, a superposition of at least one zone of a conductive layer (aluminum) formed on the front face and constituting the test pad, and a zone of another conductive layer formed on the rear face and constituting the connection pad. One can even have a superposition of several metal layers formed on the front face, connected to each other and the same geometry as the test pad and the connection pad.
    Since some connection pads will have to pass a large current (for example the general power pads), it is expected that the connection between the different superimposed pads is with large vias or with multiple conductive vias between layers.
    However, these multiple vias are quickly annoying because they create reliefs that can weaken the subsequent welding of a wire on the stud. The reliefs are due to the fact that the etching of the thinned silicon, to allow access to the conductive layers etched on the front face, is a chemical etching forming oblique flank holes in which the aluminum descends to come into contact with a layer conductive.
    However, we realized that it is sufficient to provide a small number of vias drivers (1 to 4) even if the current we want to pass is important, provided that these vias are sufficiently elongated. Indeed, the overall resistivity of the vias is related more to the length of the vias than to their surface for a given thickness of metal of the stud. This results from the fact that the metal is deposited in approximately constant thickness in the vias and that it is the small thickness of the metal which generates a significant electrical resistance even if the via has a large surface.
    The object of the invention is to propose a stud configuration which facilitates the connection of a welded wire to a small footprint pad and which allows the connection pads to be tested by the rear face with the same configuration of test tips which will have served in the test by the front.
    Therefore, according to the invention, there is provided an electronic component comprising an integrated circuit formed on the front face of a first thinned semiconductor substrate, the thinned substrate comprising a thin semiconducting layer of about 2 to 10 micrometers in thickness. first substrate being mounted by its front face on a transfer substrate, the component comprising - on the front face of the first substrate a test pad constituted by a zone of a conductive layer deposited on the front face, and on the face back, accessible, of the semiconductor layer, an outer connection pad formed by a portion of metal layer deposited on this rear face, superimposed on the test pad and electrically connected to the test pad via at least one elongated opening hollowed out in the thickness of the thinned semiconductor layer, opening into which the metal layer penetrates, the connection pad having the general shape e of a rectangle (the rectangular word is considered here as also including the square) having a first flat surface portion for welding an outer lead wire and at least a second surface portion in which the opening is located elongate, characterized in that the semiconductor layer has no opening below the first flat surface portion and in that said first portion comprises at least one continuous portion in which a circular disk occupying at least 50 % of the surface of the rectangle.
    The first flat surface portion is the one on which a connection wire will be welded at the time of packaging of the integrated circuit chip; the openings or conducting vias are not located in this portion; the circular part of this surface represents the surface available in practice for fixing the wire by centering it correctly on the stud. The resulting stud configuration is a compact configuration. It makes it possible to prevent the recessed reliefs resulting from the etching of vias between the connection pad and the underlying layers to hinder the subsequent soldering of a connection wire. It allows superposition, without excessive space, of the test pad and the connection pad, and thus allows a test under spikes with the same configuration of test points for the front and the back.
    As will be seen, several practical configurations can be adopted according to the invention, and in particular one of the following preferred configurations: the stud has a slightly rectangular shape, with a side having a length of between 5 and 20% more that the other, the elongated opening extending along a short side of the rectangle, parallel to this side; the continuous circular portion can then typically occupy from 75% to 65% of the surface of the rectangle; or the opening extends along the two short sides of the rectangle, parallel to these sides, and the circular portion may occupy from 65% to 70% of the surface of the rectangle; the stud has a square shape and the elongate opening extends along two adjacent edges of the square, parallel to these edges; the circular portion can then occupy 60% to 70% of the surface of the pad; the width of the elongated opening is preferably between 2% and 9% of the square side; the stud has a square shape and the elongated opening is distributed along four adjacent edges of the square, parallel to these edges; the circular portion can occupy an area of 55% to 65% of that of the rectangular pad; the width of the elongated opening is preferably between 1% and 5% of the square side; - The pad has a square shape and the elongated opening is divided into four disjoint portions each located at a respective corner of the square; the circular part can occupy from 55% to 65% of the stud.
    Other features and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the appended drawings, in which: FIG. 1 represents in section an integrated circuit structure on a thinned substrate, with a connection pad provided with vias distributed under the pad, connecting the pad to underlying conductive layers; FIG. 2 represents a view from above of the connection pad of FIG. 1; - Figure 3 shows in section a stud structure according to the invention; - Figures 4 to 8 show, in top view several configurations of connection pads according to the invention.
    Figures 1 and 2 show an example of a possible structure for a connection pad of an electronic component. The electronic component is an integrated circuit formed in a thinned semiconductor substrate 12 bonded to a transfer substrate 20. The substrate is in principle silicon. The component may in particular be an image sensor intended to be illuminated by the rear face of the thinned substrate.
    The back side is the one facing towards the top of FIG. 1. the front face is facing downwards. In the manufacturing process there are first manufacturing steps from the front face, in particular doping, deposits and etchings of conductive and semiconducting insulating layers, then a bonding of the semiconductor substrate by its front face on the transfer substrate 20, then a thinning of the semiconductor substrate 12 by its rear face to a semiconductor thickness of a few microns, typically from 2 to 5 microns, and finally manufacturing steps from the back side. Figure 1 shows a schematic sectional view of the component at this stage of manufacture. After the processing steps by the rear face, it will remain to mount the component in a housing by welding connecting son between the connection pads of the component and the pads of a housing.
    In the front-panel manufacturing steps, an alternation of several levels of conductive (usually metallic, for example aluminum) and insulating (usually silicon oxide) layers is formed. The various conductive layers are etched to define patterns of internal connections in the integrated circuit; the insulating layers are etched to define openings for establishing conductive vias between the conductive layers of different levels, depending on the connections to be made between these layers. An insulating layer of passivation covers all the metal levels; this layer has a planar surface in close contact with the transfer substrate 20.
    The metal conductive layers are designated by the references M1, M2, M3, M4 in the order in which they are deposited on the semiconductor substrate during front-end processing; it will be noted that the first deposited layer is M1 and the last one is M4, knowing that the substrate 12 is shown turned face down in FIG.
    The set of insulating layers in which the metal layers M1 to M4 are embedded is designated by the reference 14.
    The right part of Figure 1 shows a possible constitution of a connection pad 30 of the component. It is formed mainly by a metal layer (in principle aluminum) deposited and etched on a portion 22 of the semiconductor substrate. The metal deposit is made by the rear face of the substrate. The portion 22 is electrically insulated from the rest of the substrate 12 by a trench 24 which completely surrounds this portion. This trench is hollowed out by the rear face over the entire thickness of the thinned semiconductor substrate 12, as far as the insulating layer 14.
    The connection pad 30 is electrically connected to the underlying integrated circuit, and more specifically to at least one of the conductive layers M1 to M4, by conductive vias 32 distributed under the surface of the pad. The conductive vias are openings through the entire thickness of the thinned substrate 12 and a portion of the thickness of the insulating layer 14 to reach a conductive layer formed from the front face. These openings are filled with the metal (aluminum) deposited to form the stud 30. In the example shown, the conductive vias 32 come into physical contact with the first conductive layer M1, and portions of layers M1, M2, M3, and M4. are located below the stud 30 and have substantially the same geometry and the same horizontal position as the pad 30. These layers are interconnected by other conductive vias 34 distributed over the surface area corresponding to this geometry.
    FIG. 2 represents a top view of a possible configuration of the conductive vias 32 distributed on the surface of the connection pad 30.
    The presence of conductive vias creates a relief on the surface of the stud, especially when the silicon substrate is etched by a chemical etching process. This relief essentially comprises hollows in the center of the conductive vias. If the vias are elongated, the recessed surfaces follow the direction of elongation.
    These reliefs can affect the quality of the solder wire connection that will be welded to the pad.
    Figures 3 and 4 show a component having a stud structure according to the present invention.
    The openings or conductive vias distributed under the surface of the stud are replaced, in this embodiment, by a single elongate via 32 extending over almost the entire length of one side of the stud. The stud is slightly rectangular with a small side of width A and a large side of width B. The via extends along a short side. It can therefore be considered that the stud has a first portion of square surface A side which is a flat surface, devoid of conductive vias, and a second portion of rectangular surface BA width and length A which is not uniformly flat and which has a recessed relief due to via.
    The flat square surface portion is reserved for the welding of a connection wire, and it can be considered that in this square surface is inscribed a circular disk of diameter D = A (hatched in the figure) which is more specifically reserved for the welding of the wire and which must have a minimum dimension to allow such a weld in a reliable and reproducible manner.
    According to the invention, the stud is constituted so that the surface Sc of the circular disk (Sc = DD2 / 4) inscribed in the flat surface and available for a wire solder occupies at least 50% and preferably between 60% and 75%. % of the total area St of the rectangular pad (St = AxB).
    Preferably, in the configuration of FIG. 4, the width B-A of the residual surface available for accommodating the elongated via extends over a width equal to approximately 5% to 20% of the small side A of the pad. The pad then occupies an area 5% to 20% greater than the area (A2) of a square pad whose vias would be entirely located under the circular welding zone.
    In a case where it would be necessary to pass more current still in the conductive via, one can adopt a configuration with two elongated vias, either as in Figure 5 (an elongated via along the edge of each of the two short sides of the rectangular pad ), as in Figure 6 (a respective elongated via along two adjacent edges of a square pad).
    With the configuration of FIG. 5, it is preferable to choose a pad surface such that the surface Sc of the circular disk occupies between 65% and 70% of the surface St of the pad, and for this, the residual width of each side to accommodate a respective via will be (BA) / 2 equal to about 5% to 10% of the value A of the small side of the pad. The pad then occupies an area 10% to 20% greater than that it would occupy if the vias were located under the weld zone.
    In the configuration of Figure 6, the pad is square, A = B, and D is less than A; a pad surface is preferably provided such that the surface Sc of the circular disk (St = DD2 / 4) occupies between about 60% and 70% of the surface St = B2 of the pad; for this, the residual width B-D available to house the vias is about 5% to 14% of the diameter D.
    The vias are shown separated in Figure 6, but they could be joined at the corner where they are adjacent.
    If the lengths of narrow vias are not enough yet we can still try to place a via on three or four sides of the stud, the center of the stud containing the disk reserved for welding. Figure 7 shows a configuration with four vias each lengthened along one side of the stud. The stud is a square of side B greater than the diameter D of the disc. The width reserved for vias is (B-D) / 2 and is expected to be about 5 to 10% of D; the circular surface reserved for the disk is then about 55% to 65% of the surface of the pad.
    In all the configurations of Figures 4 to 7, the elongated vias occupy substantially the entire length of one side of the stud.
    Finally, Figure 8 shows a solution to best use the corners of the stud. The elongated conductive vias are not parallel to the edges of the stud (which is preferably square) but rather housed in the corners, in the space left free beyond a circle of diameter D. The B side is slightly greater than the diameter D. The surface St of the disk of diameter D is then preferably between 55% and 65% of that of the pad. In the drawing of Figure 8, the vias have a rounded shape extending parallel to the circular surface; they could also be L-shaped or triangle shaped.
    The connection pad of FIG. 3, having in plan view one of the configurations of FIGS. 4 to 8, preferably overhangs metal strips having substantially the same surface and the same horizontal position as pad 30. These metal pads are formed in the various conductive layers M1 to M4 and are electrically joined by vias 34 as in Figure 1. The vias 34 may be distributed over the entire surface of these beaches and be numerous and very small. They are indeed etched in insulating layers by processes that do not create oblique flank openings (unlike silicon etching) and in any case they are not used to solder a wire connection.
    During manufacture, these metal pads in the form of pads can be used as test pads for test operations under spikes. In particular, the conductive layer M4 preferably comprises a zone constituting a test pad 40 to allow a test after the end of the manufacturing steps by the front face, before depositing an insulating layer of passivation and planarization on the front face . Given the identical geometry of the connection pads and the test pads, the configuration of the test tips may be the same for the front-end tests and the back-end tests (provided that the entire chip has a symmetry of arrangement of the pads).
    In the configuration of Figure 2, there is shown a connection pad 30 which overhangs the metal pads. It would also be possible to use a configuration in which the pad is partially offset laterally with respect to the metal pads or to the test pad (the connection via 32 remaining of course above the metal pad that it must contact). This does not prevent the configuration of test points can be the same front and rear face, for example by providing that all pads are deported in the same direction and the same amount.
    权利要求:
    Claims (10)
    [1]
    An electronic component having an integrated circuit formed on the front face of a first thinned semiconductor substrate (12), the thinned substrate having a thin semiconductor layer of about 2 to 10 micrometers thick, the first substrate being mounted by its front face on a transfer substrate (20), the component comprising - on the front face of the first substrate a test pad (40) consisting of a zone of a conductive layer (M4) deposited on the front face, and on the rear face, accessible, of the semiconductor layer, an outer connection pad (30) formed by a portion of metal layer deposited on this rear face, superimposed on the test pad (40) and electrically connected to the test pad by the intermediate of at least one elongated opening (32) hollowed out throughout the thickness of the thinned semiconductor layer, opening into which the metal layer penetrates, the connection pad (30) having the generic shape a rectangle having a first portion of planar surface for welding an outer lead wire and at least a second surface portion in which the elongate opening is located, characterized in that the semiconductor layer is devoid of opening below the first portion of flat surface and in that the first portion comprises at least one continuous portion in which can register a circular disk occupying at least 50% of the surface of the rectangle.
    [2]
    2. Electronic component according to claim 1, characterized in that the stud has a generally rectangular shape, with one side having a length (B) between 5 and 20% more than the other (A), the elongated opening extending along a short side of the rectangle, parallel to that side.
    [3]
    3. Electronic component according to claim 1, characterized in that the stud has a rectangular shape, and the surface of the circular portion occupies from 75% to 65% of the surface of the rectangle
    [4]
    An electronic component according to claim 1, characterized in that the stud has a rectangular shape, with one side having a length of between 5 and 20% more than the other, the elongate opening extending along the two small sides of the rectangle, parallel to these sides.
    [5]
    5. Electronic component according to claim 1, characterized in that the stud has a rectangular shape, the elongate opening extending along the two short sides of the rectangle, parallel to these sides and the surface of the circular portion occupies 65 at 70% of the surface of the rectangle.
    [6]
    6. Electronic component according to claim 1, characterized in that the stud has a square shape and the elongated opening extends along two adjacent edges of the square, parallel to these edges, over a width of between 2% and 9. % of the square side.
    [7]
    7. Electronic component according to claim 1, characterized in that the stud has a square shape and the elongate opening extends along two adjacent edges of the square, parallel to these edges, and the surface of the circular portion occupies between 60% and 70% of the surface of the stud.
    [8]
    8. Electronic component according to claim 1, characterized in that the elongated opening is distributed along four adjacent edges of the square, parallel to these edges, over a width of between 1% and 5% of the square side.
    [9]
    9. Electronic component according to claim 1, characterized in that the elongate opening is distributed along four adjacent edges of the square, parallel to these edges, and the surface of the circular portion occupies 55% to 65% of the surface area. of the plot.
    [10]
    10. Electronic component according to claim 1, characterized in that the stud has a square shape and the elongated opening is divided into four disjoint portions each located at a respective corner of the square, the circular portion occupying from 55% to 65% of the surface of the stud.
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    JP6649189B2|2016-06-27|2020-02-19|ルネサスエレクトロニクス株式会社|Semiconductor device|
    法律状态:
    2018-02-28| HC| Change of name of the owners|Owner name: TELEDYNE E2V SEMICONDUCTORS SAS; FR Free format text: DETAILS ASSIGNMENT: CHANGE OF OWNER(S), CHANGEMENT DE NOM DU PROPRIETAIRE; FORMER OWNER NAME: E2V SEMICONDUCTORS Effective date: 20180115 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR0903795A|FR2948815B1|2009-07-31|2009-07-31|CONNECTION PLATE STRUCTURE FOR ELECTRONIC COMPONENT|
    FR0903795|2009-07-31|
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